• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD The modalities that allow the interconnection of multiple chips using organic bridges are described. In some embodiments, an organic package substrate has a built-in organic bridge. The organic bridge may have interconnecting structures that allow the matrix wiring to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metallic targeting layer, a metallic filler layer, intercalated organic polymeric dielectric layers, but without a substrate layer. Embodiments having only a few layers can be embedded in the top layer or a few top layers of the organic package substrate. Manufacturing methods are also described.
    公开号:BR102013032406B1
    申请号:R102013032406-0
    申请日:2013-12-17
    公开日:2021-05-25
    发明作者:Mihir K. Roy；Stefanie M. Lotz；Wei-Lun Kane Jen
    申请人:Intel Corporation；
    IPC主号:
    专利说明:

    [0001] This application claims the priority benefits of U.S. Patent Application No. 13/722,203, filed December 20, 2012, which is incorporated herein by reference in its entirety. Technical Field
    [0002] Modalities pertain to integrated circuit (IC) arrays, multi-chip packages, and associated methods. More particularly, the embodiments pertain to using an organic bridge on an organic package substrate to interconnect the matrices with a high density interconnect. BACKGROUND
    [0003] In order to improve performance, processing unit products are increasingly integrated into multiple arrays within the processing unit package in a side-by-side or other multi-chip module (MCM) format. In the traditional MCM format, the chip matrix is interconnected through connections within the substrate. One way to increase the input and output (IO) capacity is to connect the array through the built-in IO bridge featuring a very high wiring density locally between the array. Formatting dense metal characteristics on a silicon substrate is the conventional fabrication approach. This allows for consistent size tail end metallization of very fine feature and a large number of IO interconnects. However, there is a significant mismatch between coefficient of thermal expansion (CTE) of an organic package and a silicon bridge, leading to delamination and cracking between multiple materials. With multiple process steps used in MCM production after the silicon bridge is located in the substrate, the actual fabrication process can result in cracking and delamination. Additionally, embedding an outer bridge made of silicon to increase the local IO makes the silicon bridge ultra-thin and embedding the silicon bridge into the substrate can be a challenge. Brief Description of Drawings
    [0004] FIG. 1 illustrates a general microelectronic process according to some modalities; FIG. 2 illustrates a plan view of a microelectronic package according to some embodiments; FIG. 3 illustrates a cross-sectional view of an organic bridge located within a substrate according to some embodiments; and FIG. 4 illustrates a process for creating an organic bridge according to some modalities. Detailed Description
    [0005] The following description and drawings sufficiently illustrate specific modalities to enable those skilled in the art to practice them. Other modalities may incorporate structural, logical, electrical, process, and other changes. Parts and characteristics of some modalities may be included or replaced by those of other modalities. The embodiments presented in the claims encompass all available equivalences of those claims.
    [0006] FIG. 1 illustrates a general microelectronic process according to some modalities. The process, generally illustrated at 100, collects the assemblies made from a substrate fabrication process 102, a bridge fabrication process 104 and assembles them as illustrated by 108 to produce a microelectronic device package such as a multi-chip package 110.
    [0007] The matrix fabrication process 106 is illustrated in dashed form to indicate that the matrix can be assembled on the substrate and the bridge in the same process 108 or in a separate process later. The die manufacturing process 106 can be any process sufficient to produce the desired dies that will be incorporated into the final product. No further description of die fabrication 106 will be provided as it is unimportant to the description presented here.
    [0008] The substrate 102 manufacturing process can comprise any process of producing a suitable packaged substrate that can be used, for example, in multi-chip packaging. The separate substrate fabrication process 102 allows the process to be effectively tuned to the particular package substrate. In general, this means that the packet substrates and process 102 can only be customized for the aspects triggered by the packet substrate (and bridging) and not the aspects triggered by the bridge itself. In general, this allows for the use of a less expensive process, a process that provides greater throughput, greater volume, more relaxed conductor geometries in and within the package substrate, a combination of all of the same, or some other criteria or particular combination of criteria. Typically packaged substrates are made from an organic polymer such as epoxy. Package substrates can have a variety of materials such as silica, calcium oxide, magnesium oxide, etc., added to the organic polymer to achieve particular properties such as the desired glass transition temperature or other desired properties.
    [0009] The package substrates produced by the Substrate 102 manufacturing process can include various layers and geometries such as wires and connection points. In one example, substrates can be produced using design rules of about 40 µm wire width and about 40 µm wire spacing. Similarly, build-up layers, if any, can be thicker than those used by the 104 bridge fabrication process to produce organic bridges.
    [00010] The bridge fabrication process 104 may comprise a process for producing a high density interconnect bridge suitable for placement on the package substrate. An illustrative process is discussed in conjunction with FIG. 4 below. Bridges can be made of an organic polymer such as an epoxy without its own substrate (eg with only a few build-up layers or a single build-up layer comprising the targeting and infill layers). In one embodiment the organic bridges produced by the 104 bridge fabrication process are less than 30 µm thick. In another modality, the organic bridges produced by the 104 bridge fabrication process are about 15 µm thick.
    [00011] In bridge arrangements that do not have any substrate, when the bridge is placed on the package substrate as part of the assembly process 108, the bridge conforms to the contours of the layer on the package substrate under it. This helps to minimize intermaterial issues such as cracking, splintering or delamination. The thinness of the bridge makes it easy to satisfy any z height requirements of the process and/or package. For modalities manufactured without a substrate, the bridge fabrication process 104 can utilize economical and reusable glass carriers.
    [00012] The organic polymer used in the 104 bridge fabrication process for the production of organic bridges can be the same as, or different from, the substrate organic polymer. Since both materials are organic, organic bridges have better interfacial adhesion (compared, for example, to bridges made from silicon). Since both materials are organic, cracking, chipping and delaminating and other problems associated with using different materials can be minimized.
    [00013] The 104 bridge fabrication process can be designed to produce small high density geometries in the bridge to carry the high density IO interconnects. In one embodiment, the organic bridge fabrication process 104 uses design rules of about 3 µm or less wire width and about 3 µm or less wire spacing. In another embodiment, the organic bridge fabrication process 104 uses wax design rules of 3 µm or less wire width and spacing in some areas or layers and larger wire width and spacing in other areas or layers of the bridge (by example, about 10 µm wire width and about 10 µm wire spacing).
    [00014] FIG. 2 illustrates a plan view of a microelectronic package according to some embodiments. Package 200 has a package substrate 212 and an organic bridge 214 embedded in package substrate 212. Package substrate 212 may comprise an organic polymer such as an epoxy. Package substrate 212 may also comprise an organic polymer such as epoxy. The organic polymer of organic bridge 214 may be the same as, or different from, the organic polymer of package substrate 212.
    [00015] The organic bridge 214 comprises an interconnecting structure 216 located at a location 220 and an interconnecting structure 218 located at a location 222. The interconnecting structure 216 and the interconnecting structure 218 may comprise a plurality of connection points, such as the connection point illustrated as 208. The various connection points within the interconnecting structure 216 and 218 are connected by conductive paths. In FIG. 2, illustrative conductive paths are illustrated at 210. Connections between the various connection points are suitable for the matrix that will be interconnected by organic bridge 214. Locations 220 and 221, illustrated by dashed lines, indicate the locations in which the matrix interconnected by organic bridge 214 will be located.
    [00016] Interconnecting structures 216 and 218 in an organic bridge 214 are typically located toward one end of organic bridge 214. Thus, locations 220 and 222 are typically toward the ends of organic bridge 214. the location of interconnecting structures 216 and 218 is determined by the matrix that will be interconnected by organic bridge 214.
    [00017] The microelectronic package 200 may comprise multiple organic bridges 214, each having multiple interconnecting structures 216 and 218 in order to interconnect multiple arrays. In FIG. 2, additional organic bridges are illustrated by 202, interconnecting structures are illustrated by 204, and matrix placement locations are illustrated in dashed lines by 206. These organic bridges 202 may be similar to organic bridge 214. The interconnecting structures 204 may be similar to interconnecting structure 216 and/or interconnecting structure 218.
    [00018] FIG. 3 illustrates a cross-sectional view of an organic bridge 202 located within a substrate according to some embodiments. The assembly, illustrated generally at 300, may comprise a substrate 302 and an organic bridge 304. The substrate 302 may be a package substrate 302, such as that manufactured by the substrate 102 fabrication process of FIG. 1 and may comprise an organic polymer such as an epoxy.
    [00019] Substrate 302 may comprise connection points 306 to connect a matrix, such as a matrix 318 and 319 to substrate 302. Connection points 306 and associated conductive path (not shown) may adhere to appropriate design rules for the substrate 302. In one embodiment, the design rules of substrate 302 allow for larger geometries (for eg connection points 306) than the design rules of embedded organic bridge 304. In one example, substrate 302 can be produced using the design rules of a wire width of about 40 µm and a wire spacing of about 40 µm. Similarly, the building layers, if any, may be thicker than in organic bridge 304.
    [00020] The 302 substrate has a recess to receive the 304 organic bridge. Depending on the thickness of the dielectric and other layers of the 302 substrate and the thicknesses of the 304 organic bridge, the recess may only need to extend into the outermost or multiple layer outermost layers. Such a recess can be formed within substrate 302, for example, by using laser writing.
    [00021] The 304 organic bridge may comprise an organic polymer such as an epoxy. The organic polymer of organic bridge 304 may be the same as, or different from, the organic polymer of substrate 302. For clarity, some of the various layers of organic bridge 304 are illustrated in various patterns so that they can be distinguished from surrounding items.
    [00022] The 304 organic bridge is located in a 302 substrate recess using an organic polymer to adhere to the 304 organic bridge within the recess. The organic polymer can be a matrix bonding film, an epoxy, or any other type of organic polymer that sufficiently adheres organic bridge 304 to substrate 302. In FIG. 3, organic bridge 304 bonding to substrate 302 is illustrated at 308. Since substrate 302 and organic bridge 304 both comprise an organic polymer, layer 308 can adhere organic bridge 304 to substrate 302 in a manner that minimizes problems arising from the interface of two different materials such as chipping, cracking and delamination.
    [00023] The organic bridge 304 is depicted in FIG. 3 by layer 310, 312 and 314 and 316. Layer 310 represents a metallic layer within organic bridge 304, which may be included as part of bridge 304. Layer 314 represents a metal targeting layer embedded within dielectric layer 312 In FIG. 3, the joining of organic bridge 304 to substrate 302 is illustrated at 308. Since substrate 302 and organic bridge 304 both comprise an organic polymer, layer 308 can adhere organic bridge 304 to substrate 302 in a manner that minimizes problems arising from the interface of two different materials such as chipping, cracking and delamination.
    [00024] The organic bridge 304 is depicted in FIG. 3 by layer 310, 312 and 314 and 316. Layer 310 represents a metallic layer within organic bridge 304, which may be included as part of bridge 304. Layer 314 represents a metal targeting layer embedded in dielectric layer 312. Dielectric layer 312 comprises an organic polymer such as an epoxy and represents intercalated dielectric layers 312. Layer 316 represents a filler layer in which, for example, interconnecting structures 204 may be formed as part of organic bridge 304. In one embodiment, the design rules for organic bridge 304 comprise a wire width of about 3 µm or less, and a wire spacing of 3 µm or less. In another embodiment, the design rules for organic bridge 304 comprise about 3 µm or less of wire width and spacing in some areas or layers and larger wire width and spacing in other areas or layers of the bridge (e.g., about 10 µm wire width and about 10 µm wire spacing).
    [00025] Some modalities of organic bridge 304 do not have any substrates 302. Such modalities may comprise targeting and filler layers 314 and 316, and possibly some additional metallic layers all with intercalated dielectric layers 312, but without, for example, a substrate 302 No 302 substrates means that some embodiments of the 304 organic bridge do not have any layer that has substantial silicon content. In such embodiments, any "substrate" layer will be made substantially of a metal or an organic polymer such as an epoxy. The organic polymer can include various additives such as silica, calcium oxide, magnesium oxide, or other additives to modify certain desired properties of the organic polymer.
    [00026] In one embodiment, the organic bridge 304 does not have any substrate 302 and is about 15 µm thick. In another embodiment, organic bridge 304 has no substrate 302 and is less than about 20 µm thick. In another embodiment, organic bridge 304 has no substrate 302 and is less than about 30 µm thick. Since organic bridge 304 does not have any substrate 302, it tends to conform to the contours of the recess within which it is located. In such embodiments, the lack of a substrate 302 and the thickness of the organic bridge 304 allows the organic bridge 304 to be incorporated into a solder mask cavity in the surface layer of the substrate 302 and very thin slope matrices can be directly connected by union based on thermocompression.
    [00027] FIG. 4 illustrates a process for creating an organic bridge 304 according to some embodiments. Such a process can be used, for example, in the bridge fabrication process 104 of FIG. 1. In FIG. 4, the process generally illustrated as 400 is a glass rotation (SoG) technique. SoG has the ability to provide a finer trace and spacing than other processes, and as such is illustrated here. However, other processes can also be used.
    [00028] In 402 a silicon and glass carrier plate is obtained. Since the inlet carrier plate will not form part of the final organic bridge 304, economical and reusable carrier plates can be used for the process.
    [00029] At 404 a release layer and lower dielectric layer (SoG) is deposited. As previously described, dielectric layer 312 comprises an organic polymer such as an epoxy.
    [00030] In 406, the deposition of the seed layer occurs, for example, by spraying a dry sandpaper resistance element (DFR) and the standardization of the seed layer also occurs.
    [00031] In 408, coating occurs along with DFR removal and application of the next 312 dielectric layer using SoG techniques.
    [00032] In 410, pathway formation occurs along with seed layer deposition using, for example, spraying. DFR application and standardization also take place.
    [00033] At 412, the resulting assembly is released from the carrier plate and bridge separation (eg, separating the assembly into individual organic bridges 304) takes place.
    [00034] In general, organic bridges 304, such as those described in conjunction with figures 1 to 3, have only a reduced thickness, perhaps only the targeting layer 314, infill layer 316, ground and reference layers for signal layers, plus intercalated dielectric layers 312. In such a situation, this 304 double layer organic bridge will be about 15 µm thick. However, if desired, the process illustrated in 408 and/or 410 can be repeated as suitable to achieve a perhaps three or four layer organic bridge 304 having a thickness of from about 20 µm to about 30 µm.
    [00035] The above detailed description includes references to the attached drawings, which form a part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the description can be practiced. These modalities are also referred to here as "examples". Such examples may include elements in addition to those illustrated or described. However, the present inventors also contemplate examples in which only those illustrated or described elements are provided. Furthermore, the present inventors also contemplate examples using any combination or interchange of these illustrated or described elements (or one or more aspects thereof) with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) illustrated or described herein.
    [00036] In this document, the terms "a", or "an" are used, as is common in patent documents, to include one or more of them, regardless of any other case or use of "at least one" or " one or more". In that document, the term "or" is used to refer to a non-exclusive or, such as "A or B" includes "A but not B", "B but not A" and "A and B", a unless otherwise indicated. In this document, the terms "including" and "in which" are used as simple language equivalents of the respective terms "comprising" and "wherein". Furthermore, in the following claims, the terms "including" and "comprising" are open ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed following a term in a claim is still considered to be included in the scope of that claim. Furthermore, in the following claims, the terms "first", "second", and "third", etc. they are used merely as labels, and should not impose numerical requirements on their objects.
    [00037] The above description should be illustrative rather than restrictive. For example, the examples described above (or one or more aspects thereof) can be used in combination with one another. Other modalities may be used, such as by a person skilled in the art after reviewing the above description. The Abstract is provided to conform to 37 C.F.R § 1.72(b), to allow the reader to readily determine the nature of the technical description. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the Detailed Description above, several features can be grouped together to give a rationale to the description. This is not to be interpreted as implying that an unclaimed described feature is essential to any claim. Rather, the present inventive subject may meet less than all the features of a particular described embodiment. Accordingly, the following claims are incorporated herein into the Detailed Description, with each claim being independent as a separate embodiment, and it is contemplated that such embodiments may be combined with one another in various combinations or permutations. The scope of the inventive material shall be determined by reference to the appended claims, together with the full scope of equivalences to which such claims are entitled.
    权利要求:
    Claims (12)
    [0001]
    1. Microelectronic package (200) characterized by the fact that it comprises: an organic polymeric substrate (212); an organic polymeric bridge (214) embedded in the substrate, the organic polymeric bridge comprising: - a metallic targeting layer (314); - a metallic filling layer (316); - intercalated organic polymer dielectric layers (312); - a first high density interconnect structure (204) at a first location of the organic polymeric bridge, the first interconnect structure adapted to connect to a first matrix; - a second high density interconnect structure (204) at a second location of the organic polymeric bridge, the second interconnect structure adapted to connect to a second matrix; - an electrically conductive path in the organic polymeric bridge connecting the first high-density interconnect structure to the second high-density interconnect structure; and - wherein the organic polymeric substrate contains a recess and the organic polymeric bridge is embedded in the recess and joined thereto using an organic polymer.
    [0002]
    2. Microelectronic package according to claim 1, characterized in that strands of the organic polymeric substrate have a first strand width and a first strand spacing and wherein strands of the organic polymeric bridge have a second strand width and a second wire spacing.
    [0003]
    3. Microelectronic package according to claim 1 or 2, characterized in that the first wire width is greater than the second wire width and the first wire spacing is greater than the second wire spacing.
    [0004]
    4. Microelectronic package according to any one of claims 1 to 3, characterized in that the organic polymer bridge has a total thickness of less than 20 µm.
    [0005]
    5. Organic polymeric bridge adapted to interconnect a plurality of matrices, the organic polymeric bridge characterized in that it comprises: a metallic targeting layer; a metallic filling layer; intercalated organic polymer dielectric layers; and a first high density interconnect structure (204) at a first location of the organic polymeric bridge, the first interconnect structure adapted to connect to a first matrix; a second high density interconnect structure (204) at a second location of the organic polymeric bridge, the second interconnect structure adapted to connect to a second matrix; an electrically conductive path in the organic polymeric bridge connecting the first high-density interconnect structure to the second high-density interconnect structure; and wherein the organic polymeric bridge is adapted to be recessed into an organic polymeric substrate and joined thereto using an organic polymer.
    [0006]
    6. Organic polymeric bridge, according to claim 5, characterized in that all layers have a combined thickness of less than 30 µm.
    [0007]
    7. Organic polymeric bridge, according to claim 5, characterized in that all layers have a combined thickness of 15 μm.
    [0008]
    8. Organic bridge, according to any one of claims 5 to 7, characterized in that it further comprises an additional metallic layer and an additional intercalated organic polymer dielectric layer.
    [0009]
    9. Method characterized in that it comprises the steps of: providing an organic polymeric bridge comprising: - a metallic targeting layer; - a metallic filling layer; - intercalated organic polymer dielectric layers; - a first high density interconnect structure (204) at a first location of the organic polymeric bridge, the first interconnect structure adapted to connect to a first matrix; a second high density interconnect structure (204) at a second location of the organic polymeric bridge, the second interconnect structure adapted to connect to a second matrix; an electrically conductive path connecting the first high-density interconnect structure to the second high-density interconnect structure; providing an organic package polymeric substrate having a recess formed therein; and embedding the organic polymeric bridge in the recess of the organic package polymeric substrate, joined thereto using an organic polymer.
    [0010]
    10. Method according to claim 9, characterized in that all layers of the organic bridge have a thickness of less than 15 µm.
    [0011]
    11. Method according to claim 9, characterized in that all layers of the organic bridge have a thickness of less than 20 µm
    [0012]
    12. Method according to any one of claims 9 to 11, characterized in that the metallic filling layer comprises a plurality of interconnections and wherein the method further comprises joining a first matrix to one of the plurality of interconnections and joining one second matrix to another of the plurality of interconnects, the union of the first matrix and the second matrix being performed using union based on thermocompression.
    类似技术:
    公开号 | 公开日 | 专利标题
    BR102013032406B1|2021-05-25|microelectronic package, organic polymer bridge and method
    TWI536519B|2016-06-01|Semiconductor package structure and manufacturing method thereof
    US7215018B2|2007-05-08|Stacked die BGA or LGA component assembly
    CN101409266B|2011-11-16|Package structure
    US7245021B2|2007-07-17|Micropede stacked die component assembly
    CN107851615A|2018-03-27|Independent 3D is stacked
    US20100246141A1|2010-09-30|Electronic package and method of fabrication thereof
    CN104051365A|2014-09-17|A chip arrangement and a method for manufacturing a chip arrangement
    US20130228932A1|2013-09-05|Package on Package Structure
    KR20170136934A|2017-12-12|Semiconductor package including heat spreader and methods for manufacturing the same
    BR112016004369B1|2021-02-09|method to produce a stacked semiconductor device and stacked semiconductor device
    WO2010111825A1|2010-10-07|Electronic package and method of fabrication thereof
    TW201113998A|2011-04-16|Semiconductor package with sectioned bonding wire scheme
    KR20170130682A|2017-11-29|Semiconductor package including through mold ball connectors and method for manufacturing the same
    CN105742192B|2019-02-05|The method and related device of manufacture electronic device including the encapsulating of two steps
    CN104112673B|2017-06-23|Chip package base plate and preparation method thereof
    TW202107641A|2021-02-16|Package and method of forming the same
    CN103400816B|2016-08-10|Packaging part and manufacture method thereof
    同族专利:
    公开号 | 公开日
    JP2016105484A|2016-06-09|
    KR101593277B1|2016-02-11|
    JP2014140022A|2014-07-31|
    US9548264B2|2017-01-17|
    JP6677380B2|2020-04-08|
    TW201442201A|2014-11-01|
    US10672713B2|2020-06-02|
    US9236366B2|2016-01-12|
    US20190019755A1|2019-01-17|
    EP3273476A1|2018-01-24|
    KR20140080427A|2014-06-30|
    TWI556401B|2016-11-01|
    US20160133552A1|2016-05-12|
    US20170125349A1|2017-05-04|
    BR102013032406A2|2014-08-26|
    WO2014098966A1|2014-06-26|
    US20140174807A1|2014-06-26|
    US20200294924A1|2020-09-17|
    JP2018129528A|2018-08-16|
    EP2747136B1|2019-11-20|
    KR101706997B1|2017-02-15|
    EP2747136A1|2014-06-25|
    US10103105B2|2018-10-16|
    CN104037161B|2017-03-01|
    JP6572495B2|2019-09-11|
    SG2013093521A|2014-07-30|
    KR20160025536A|2016-03-08|
    CN104037161A|2014-09-10|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3436604A|1966-04-25|1969-04-01|Texas Instruments Inc|Complex integrated circuit array and method for fabricating same|
    JPS4989157A|1972-12-29|1974-08-26|
    US4054938A|1974-05-13|1977-10-18|American Microsystems, Inc.|Combined semiconductor device and printed circuit board assembly|
    US4918811A|1986-09-26|1990-04-24|General Electric Company|Multichip integrated circuit packaging method|
    US5019535A|1989-03-28|1991-05-28|General Electric Company|Die attachment method using nonconductive adhesive for use in high density interconnected assemblies|
    US5061657A|1990-07-18|1991-10-29|The United States Of America As Represented By The Secretary Of The Navy|Method of making integrated circuit to package electrical connections after encapsulation with an organic polymer|
    US5049978A|1990-09-10|1991-09-17|General Electric Company|Conductively enclosed hybrid integrated circuit assembly using a silicon substrate|
    US5198963A|1991-11-21|1993-03-30|Motorola, Inc.|Multiple integrated circuit module which simplifies handling and testing|
    US5469333A|1993-05-05|1995-11-21|International Business Machines Corporation|Electronic package assembly with protective encapsulant material on opposing sides not having conductive leads|
    JP2591499B2|1994-10-21|1997-03-19|日本電気株式会社|Semiconductor device|
    JP3583517B2|1995-09-20|2004-11-04|株式会社東芝|Valve lock management device|
    US6750091B1|1996-03-01|2004-06-15|Micron Technology|Diode formation method|
    JP3437369B2|1996-03-19|2003-08-18|松下電器産業株式会社|Chip carrier and semiconductor device using the same|
    US6314639B1|1998-02-23|2001-11-13|Micron Technology, Inc.|Chip scale package with heat spreader and method of manufacture|
    US6317331B1|1998-08-19|2001-11-13|Kulicke & Soffa Holdings, Inc.|Wiring substrate with thermal insert|
    JP2000091273A|1998-09-11|2000-03-31|Sony Corp|Manufacture of semiconductor package and structure thereof|
    US6111756A|1998-09-11|2000-08-29|Fujitsu Limited|Universal multichip interconnect systems|
    KR100470386B1|1998-12-26|2005-05-19|주식회사 하이닉스반도체|Multi-chip Package|
    JP2001223306A|2000-02-14|2001-08-17|Casio Micronics Co Ltd|Semiconductor device and manufacturing method therefor|
    JP2002084108A|2000-07-05|2002-03-22|Matsushita Electric Ind Co Ltd|Transmission line chip and its manufacturing method and multichip module|
    WO2002017392A2|2000-08-24|2002-02-28|Polymer Flip Chip Corporation|Polymer redistribution of flip chip bond pads|
    US6627978B2|2001-09-28|2003-09-30|Intel Corporation|Chip package enabling increased input/output density|
    JP4380130B2|2002-09-13|2009-12-09|ソニー株式会社|Semiconductor device|
    US7035113B2|2003-01-30|2006-04-25|Endicott Interconnect Technologies, Inc.|Multi-chip electronic package having laminate carrier and method of making same|
    US7799699B2|2004-06-04|2010-09-21|The Board Of Trustees Of The University Of Illinois|Printable semiconductor structures and related methods of making and assembling|
    JP4581768B2|2005-03-16|2010-11-17|ソニー株式会社|Manufacturing method of semiconductor device|
    US7294552B2|2005-08-29|2007-11-13|Delphi Technologies, Inc.|Electrical contact for a MEMS device and method of making|
    JP4989157B2|2006-08-31|2012-08-01|セイコーインスツル株式会社|Electric double layer capacitor|
    CN101578473B|2007-01-11|2013-04-10|松下电器产业株式会社|Light source|
    KR100888195B1|2007-08-06|2009-03-12|한국과학기술원|Fabrication Method of PCB having Embedded Active-Chips|
    US8102663B2|2007-09-28|2012-01-24|Oracle America, Inc.|Proximity communication package for processor, cache and memory|
    JP2009231635A|2008-03-24|2009-10-08|Shinko Electric Ind Co Ltd|Wiring board and its manufacturing method, semiconductor device, and its manufacturing method|
    US8064224B2|2008-03-31|2011-11-22|Intel Corporation|Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same|
    JP2009290144A|2008-05-30|2009-12-10|Toshiba Corp|Electronics, printed circuit board, and method for producing printed circuit board|
    US9082806B2|2008-12-12|2015-07-14|Stats Chippac, Ltd.|Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP|
    US8227904B2|2009-06-24|2012-07-24|Intel Corporation|Multi-chip package and method of providing die-to-die interconnects in same|
    JP2011051584A|2009-08-07|2011-03-17|Equos Research Co Ltd|Vehicle|
    US8274149B2|2010-03-29|2012-09-25|Advanced Semiconductor Engineering, Inc.|Semiconductor device package having a buffer structure and method of fabricating the same|
    US8492197B2|2010-08-17|2013-07-23|Stats Chippac, Ltd.|Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate|
    US9406587B2|2012-06-26|2016-08-02|Intel Corporation|Substrate conductor structure and method|
    US9236366B2|2012-12-20|2016-01-12|Intel Corporation|High density organic bridge device and method|
    US8866308B2|2012-12-20|2014-10-21|Intel Corporation|High density interconnect device and method|
    US20190041594A1|2017-12-07|2019-02-07|Intel Corporation|Integrated circuit package with electro-optical interconnect circuitry|US8227904B2|2009-06-24|2012-07-24|Intel Corporation|Multi-chip package and method of providing die-to-die interconnects in same|
    US9136236B2|2012-09-28|2015-09-15|Intel Corporation|Localized high density substrate routing|
    US9190380B2|2012-12-06|2015-11-17|Intel Corporation|High density substrate routing in BBUL package|
    US9236366B2|2012-12-20|2016-01-12|Intel Corporation|High density organic bridge device and method|
    US8901748B2|2013-03-14|2014-12-02|Intel Corporation|Direct external interconnect for embedded interconnect bridge package|
    US9147663B2|2013-05-28|2015-09-29|Intel Corporation|Bridge interconnection with layered interconnect structures|
    JP2014236188A|2013-06-05|2014-12-15|イビデン株式会社|Wiring board and manufacturing method therefor|
    US9041205B2|2013-06-28|2015-05-26|Intel Corporation|Reliable microstrip routing for electronics components|
    US9642259B2|2013-10-30|2017-05-02|Qualcomm Incorporated|Embedded bridge structure in a substrate|
    US20150364422A1|2014-06-13|2015-12-17|Apple Inc.|Fan out wafer level package using silicon bridge|
    JP2016021496A|2014-07-15|2016-02-04|イビデン株式会社|Wiring board and manufacturing method for the same|
    US10468352B2|2014-09-19|2019-11-05|Intel Corporation|Semiconductor packages with embedded bridge interconnects|
    US9583426B2|2014-11-05|2017-02-28|Invensas Corporation|Multi-layer substrates suitable for interconnection between circuit modules|
    US9595496B2|2014-11-07|2017-03-14|Qualcomm Incorporated|Integrated device package comprising silicon bridge in an encapsulation layer|
    US9379090B1|2015-02-13|2016-06-28|Qualcomm Incorporated|System, apparatus, and method for split die interconnection|
    US9443824B1|2015-03-30|2016-09-13|Qualcomm Incorporated|Cavity bridge connection for die split architecture|
    US10283492B2|2015-06-23|2019-05-07|Invensas Corporation|Laminated interposers and packages with embedded trace interconnects|
    US10477684B2|2015-09-25|2019-11-12|Intel Corporation|Apparatus, system, and method including a bridge device for interfacing a package device with a substrate|
    WO2017074390A1|2015-10-29|2017-05-04|Intel Corporation|Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages|
    WO2017099788A1|2015-12-11|2017-06-15|Intel Corporation|Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate|
    US9852994B2|2015-12-14|2017-12-26|Invensas Corporation|Embedded vialess bridges|
    US10886228B2|2015-12-23|2021-01-05|Intel Corporation|Improving size and efficiency of dies|
    KR101966328B1|2016-03-29|2019-04-05|삼성전기주식회사|Printed circuit board and manufacturing for the same|
    EP3437129A4|2016-03-30|2019-09-25|INTEL Corporation|Hybrid microelectronic substrates|
    US20170287838A1|2016-04-02|2017-10-05|Intel Corporation|Electrical interconnect bridge|
    WO2018004620A1|2016-06-30|2018-01-04|Qian Zhiguo|Bridge die design for high bandwidth memory interface|
    EP3479398A4|2016-07-01|2020-02-12|Intel Corporation|Molded embedded bridge for enhanced emib applications|
    KR20180016124A|2016-08-05|2018-02-14|삼성전자주식회사|Semiconductor Package|
    KR20180016890A|2016-08-08|2018-02-20|삼성전자주식회사|Printed Circuit Board, and semiconductor package having the same|
    EP3288076B1|2016-08-25|2021-06-23|IMEC vzw|A semiconductor die package and method of producing the package|
    US11183458B2|2016-11-30|2021-11-23|Shenzhen Xiuyuan Electronic Technology Co., Ltd|Integrated circuit packaging structure and method|
    US10622311B2|2017-08-10|2020-04-14|International Business Machines Corporation|High-density interconnecting adhesive tape|
    US10483156B2|2017-11-29|2019-11-19|International Business Machines Corporation|Non-embedded silicon bridge chip for multi-chip module|
    US10784202B2|2017-12-01|2020-09-22|International Business Machines Corporation|High-density chip-to-chip interconnection with silicon bridge|
    US10475767B2|2018-01-04|2019-11-12|Kabushiki Kaisha Toshiba|Electronic device|
    JP6912423B2|2018-01-04|2021-08-04|株式会社東芝|Electronic device|
    US10580738B2|2018-03-20|2020-03-03|International Business Machines Corporation|Direct bonded heterogeneous integration packaging structures|
    US11018124B2|2018-08-31|2021-05-25|Intel Corporation|Embedded memory device and method for embedding memory device in a substrate|
    TWI662676B|2018-08-31|2019-06-11|欣興電子股份有限公司|Circuit carrier with embedded substrate, manufacturing method thereof and chip package structure|
    CN111372369A|2018-12-25|2020-07-03|奥特斯科技有限公司|Component carrier with component shield and method for producing the same|
    US10957650B2|2019-08-21|2021-03-23|International Business Machines Corporation|Bridge support structure|
    CN111769101A|2020-07-09|2020-10-13|中国科学院微电子研究所|Packaging structure and packaging method based on multiple transfer boards|
    法律状态:
    2014-08-26| B03A| Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]|
    2018-11-21| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2020-02-27| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2021-04-06| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2021-05-25| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 17/12/2013, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US13/722,203|US9236366B2|2012-12-20|2012-12-20|High density organic bridge device and method|
    US13/722,203|2012-12-20|
    PCT/US2013/044440|WO2014098966A1|2012-12-20|2013-06-06|High density organic bridge device and method|
    IBPCT/US2013/044440|2013-06-06|
    [返回顶部]